Integrated circuit devices, such as, processors and memories operating at high speeds, and/or devices which use relatively long conductive interconnections, may suffer from reduced performance. In particular, overshoot signal reflection or transmission line effect problems may occur, thereby reducing performance.
For example, when a zero volt signal is changed to a five volt signal on a conductor or bus which is long in length or has a fast edge rate, and if the bus or conductive line is not properly impedance-matched, the conductive line or bus may take some time to settle to the 5 volt value from the 0 volt value due to one or more reflections taking place one or both ends of the bus.
As manufacturing techniques of semiconductor devices improve, operational speed may also increase. Typical rise times (or lead times) and fall times (or trail times) for various semiconductor manufacturing techniques are listed in the following Table 1.
TABLE 1 Manufacturing technique Rise time (on-chip) Rise time (chip to chip) CMOS .sup. 0.5-2.0 micro second 2-4 micro second Bipolar 50-200 pico second 200-400 pico second GaAs 20-100 pico second 100-250 pico second
When the rise time "tr" and the fall time "tf" are reduced by 2.5 times shorter than a data line delay time "td", the received signal to a receiver may be distorted. This is because when the input impedance and the characteristic impedance of the data line are not matched, the transmitted signal to the receiver may be reflected to the transmitter through the data line. When (2.5*td)&gt;tr or (2.5*td)&gt;tf, a transmitted signal from a transmitter may already settle to a desired level, such as a stable level of 0V or Vcc.
However, since the delay time of a data line is longer than the rise and fall time, the reflected signal to the transmitter may overlap the stable signal before the transmitting signal is transmitted to the receiver, and thereby reflecting to the input signal of the receiver. The above sequential process may repeatedly take place from the rising edge or the falling edge of the transmitting signal.
FIG. 1 is a waveform illustrating an example of ringing of the input signal of a receiving integrated circuit device or a receiver in accordance with an output signal of a transmission integrated circuit device or a transmitter during signal transmission between conventional integrated circuit devices. As shown in FIG. 1, the received signal is hardly distorted. However, the signal transmitted to the receiver may be unusable, due to ringing.
In order to reduce the above-described distortion, impedance matching may be adapted to a data line between the integrated circuit devices. Serial or parallel matching may be used.
Serial adaptation or a serial matching is provided by matching the output impedance of the transmitter to the characteristic impedance of the data line and maintaining an open state for the port near the receiver. However, the impedance of data line may be changed, so that it may be difficult to control.
Parallel matching is provided by matching the impedance of receiver to the characteristic impedance of the data line. However, in the parallel matching scheme, power in the static state may be consumed and a signal having a reduced deviation at the output port of the data line may be used. Furthermore, in parallel matching, the signal transmission between the integrated circuits may have a heterogenous structure that is difficult to match the input impedance of the receiver to the characteristic impedance of the data line.
FIG. 2 is a schematic view illustrating an example of a parallel matching scheme in conventional integrated circuit devices coupled to each other through a data line. A CMOS inverter 12 is provided in a transmitter 10 and used for an output buffer, and a CMOS inverter 16 is provided in a receiver 14 and used for an input buffer circuit.
The transmitter 10 is coupled to the receiver 14 through a data line 18. A terminal resistor 20 is coupled between a power supply level (power source) Vdd and one side of the data line 18 near the receiver 14. The terminal resistor 20 may be integrated inside the receiver 14, or may be directly coupled to the data line 18 outside the receiver. Assume the characteristic impedance Zo of the data line 18 and the resistance of the terminal resistor 20 is matched to 50 ohm, and the delay time td of the data line 18 is 1 nS (nano second).
FIG. 3A is a waveform illustrating signal V22 at a node 22 of a side of a receiver in accordance with input signal A of a transmitter in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 2. The received signal V22 is not disturbed according to the parallel matching of the above condition, thereby being similar to the transmitting signal A as shown in FIG. 3A.
FIG. 3B is a waveform illustrating dynamic current i1 at one position 1 of a transmitter output buffer and the dynamic current i2 at the other position 2 of the transmitter output buffer in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 2. FIG. 3C is a waveform illustrating the dynamic current ia of the data line in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 2.
As described above, although the received signal V22 may not be distorted by the parallel matching scheme as shown in FIG. 2, the dynamic current ia flows in the data line as shown in FIG. 3C. Therefore, the devices may consume large amounts of power during the signal transmission. Thus, the parallel matching scheme may not be adapted to low-power chip interconnection, such as are used in low-power consumption integrated circuit devices such as the processors and memories in portable computers, portable terminals, and portable telephones.
FIG. 4 is a schematic view illustrating another example of a parallel matching scheme in conventional integrated circuit devices coupled to each other through a data line. When the logic level of the input signal is changed from level 0 to 1 or from level 1 to 0, the impedance-matching scheme by a terminal device 34 is adapted to the data line between the integrated circuit devices as shown in FIG. 4. Therefore, the terminal device 34 maintains the open state when the logic level stays at 1 or 0. This scheme is called a dynamic termination DT, and is known to those skilled in the art.
As shown in FIG. 4, a transmitter 24 has a CMOS inverter 26 as the output buffer circuit, and a receiver 28 has a CMOS inverter 30 as the input buffer circuit. The transmitter 24 is coupled to the receiver 28 through a data line 32.
The terminal device 34 is coupled to one side node 40 of the data line 32 near the receiver 28 in parallel. The terminal device 34 has a resistor 36 and a capacitor 38 coupled to each other in series. The resistor 36 is coupled between the data line 32 and the capacitor 38.
FIG. 5A is a waveform illustrating a signal V40 at a node 40 of a side of the receiver in accordance with input signal A of the transmitter in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 4. FIG. 5B is a waveform illustrating the dynamic current ia of the data line in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 4.
The signal V40 of a node 40 at the side of the receiver may not be distorted as shown in FIG. 5A, but a dynamic current ia may still flow in the data line as shown in FIG. 5B. Assume that the characteristic impedance Zo of the data line 32 and resistance of the terminal device 34 are matched to 50 ohm, and delay time "td" of the data line 32 is 1 nS (nano second). The received signal V40 may not be distorted by the parallel matching of the above condition, thereby being similar to the transmitting signal A.
The capacitance of capacitor 38 in the terminal device 34 is approximately (25*td)/Zo. Hence, if the capacitance of capacitor 38 is 500 pF (pico Farad), it may be difficult to integrate the capacitor 38 into the receiver 28. Furthermore, since the parallel matching scheme as shown in FIG. 4 has a large capacitor, the dynamic current may be greatly increased as shown in FIG. 5B. The dynamic termination matching technique for resolving the above problem is described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30. NO. 9 "Low-Power Chip Interconnection by Dynamic Termination" published on Sep. 30, 1995.
FIG. 6 is a schematic diagram illustrating a further example of a parallel matching scheme in conventional integrated circuit devices coupled to each other through a data line. Referring to FIG. 6, there is shown a circuit related to the above dynamic termination DT published in the IEEE cited above. Since the circuit of FIG. 6 is described in the above-cited publication, no further explanation is necessary. According to the dynamic termination DT as shown in FIG. 6, the dynamic current may be reduced to the extent of consumption related to the above-described circuit.
FIG. 7A is a waveform illustrating signal V42 at a node 42 of a side of the receiver in accordance with input signal A of the transmitter in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 6. FIG. 7B is a waveform illustrating the dynamic current i44 of one position 44 of the transmitter output buffer and the dynamic current i46 of the other position 46 of the transmitter output buffer in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 6. FIG. 7C is a waveform illustrating the dynamic current ia of the data line in the conventional integrated circuit devices coupled to each other through the data line as shown in FIG. 6.
As can be seen from the above description, the signal may be prevented from distorting, but a large amount of dynamic current still may be consumed. According to the above described parallel matching scheme, the large amount of dynamic current may be consumed while the signal is transmitted and ringing may occur from the received signal. Also, the above described matching scheme may be adapted to 1:1 (point-to-point) data transmission, but may be difficult to adapt to 1:N (point-to-multipoint; N is 2 or more integer) data transmission because each terminal impedance may be different.